Related by context. Frequent words. (Click for all words.) 69 Open Verification Methodology 66 IEEE Std 63 PAS# [002] 62 ARM RealView 62 IEEE P#.# 62 Databahn 62 ARM7TDMI 62 Arasan Chip Systems 61 Synopsys DesignWare 61 Synplify Pro 61 Cadence Virtuoso 60 Altera FPGAs 60 SystemC models 60 ARM#EJ S 60 parasitic extraction 60 Verification IP 60 ModelSim 60 DesignWare IP 59 Advanced Switching 59 Xilinx Virtex 5 59 ISO IEC #-# [001] 59 Chip Scale 59 Host Controller 59 PureSpec 59 Custom Designer 59 Cadence Encounter 59 Cynthesizer 59 IC Validator 59 ANSI C 59 SPI#.# 58 OpenVG 58 MPLAB 58 ARM#EJ S processor 58 XAUI 58 Programmable Logic Devices 58 Quartus II 58 TRF# [002] 58 ASIC prototyping 58 Industry Processor Interface 58 IEEE #.#-# 58 WiMAX SoC 58 HSPICE 58 serdes 58 equivalence checking 58 IP XACT 58 Array FPGA 58 Natural Catastrophe Stress 58 Virtex 5 58 PacketCable TM 58 Blackfin processor 58 IP Cores 58 SystemVerilog 58 SGMII 58 AVR# [002] 58 Stratix IV GT 58 Highly Integrated 57 PHY IP 57 CMOS logic 57 Single Chip 57 Catapult C 57 PHY layer 57 JTAG Boundary Scan 57 Silicon Integration 57 custom ASICs 57 Non Volatile Memory 57 IEEE #.# [002] 57 H.#/MPEG-# AVC 57 PCIe Gen2 57 Analog Mixed Signal 57 Message Passing 57 eMMC 57 Field Programmable Gate 57 & mfrs 57 OpenGIS 57 TSMC Reference Flow 57 PowerQUICC 57 Synopsys Galaxy 57 Understanding Universal BCAR 57 Active HDL 56 Freescale i.MX# [002] 56 3GPP Release 8 56 Virtutech Simics 56 Atmel AVR 56 Reference Designs 56 Open SystemC Initiative 56 #.# micron CMOS 56 PCB layout 56 CEVA X 56 Nios II 56 xTCA 56 SysML 56 ILOG Rules 56 deviceWISE 56 Industry Smallest 56 QuickSec 56 computational lithography 56 DoDAF 56 ARM7 56 SiliconBlue 56 Physical Layer 56 ispLEVER